Personal computers and servers and the like use a hierarchy of memory devices. There is lower-tier memory, which is inexpensive and provides high storage capacity, while memory higher up the hierarchy provides high-speed operation. The bottom tier generally consists of magnetic storage such as hard disks and magnetic tape. In addition to being non-volatile, magnetic storage is an inexpensive way of storing much larger quantities of information than solid-state devices such as semiconductor memory. However, semiconductor memory is much faster and can access stored data randomly, in contrast to the sequential access operation of magnetic storage devices. For these reasons, magnetic storage is generally used to store programs and archival information and the like, and, when required, this information is transferred to main system memory devices higher up in the hierarchy.
Main memory generally uses dynamic random access memory (DRAM) devices, which operate at much higher speeds than magnetic storage and, on a per-bit basis, are cheaper than faster semiconductor memory devices such as static random access memory (SRAM) devices.
Occupying the very top tier of the memory hierarchy is the internal cache memory of the system microprocessor unit (MPU). The internal cache is extremely high-speed memory connected to the MPU core via internal bus lines. The cache memory has a very small capacity. In some cases, secondary and even tertiary cache memory devices are used between the internal cache and main memory.
DRAM is used for main memory because it offers a good balance between speed and bit cost. Moreover, there are now some semiconductor memory devices that have a large capacity. In recent years, memory chips have been developed with capacities that exceed one gigabits. DRAM is volatile memory that loses stored data if its power supply is turned off. That makes DRAM unsuitable for the storage of programs and archival information. Also, even when the power supply is turned on, the device has to periodically perform refresh operations in order to retain stored data, so there are limits as to how much device electrical power consumption can be reduced, while yet a further problem is the complexity of the controls run under the controller.
Semiconductor flash memory is high capacity and non-volatile, but requires high current for writing and erasing data operations, and these operation times are long. These drawbacks make flash memory an unsuitable candidate for replacing DRAM in main memory applications. There are other non-volatile memory devices, such as magnetoresistive random access memory (MRAM) and ferroelectric random access memory (FRAM), but they cannot easily achieve the kind of storage capacities that are possible with DRAM.
Another type of semiconductor memory that is being looked to as a possible substitute for DRAM is phase change random access memory (PRAM), which uses phase change material to store data. In a PRAM device, the storage of data is based on the phase state of phase change material contained in the recording layer. Specifically, there is a big difference between the electrical resistivity of the material in the crystalline state and the electrical resistivity in the amorphous state, and that difference can be utilized to store data.
This phase change is effected by the phase change material being heated when a write current is applied. Data is read by applying a read current to the material and measuring the resistance. The read current is set at a level that is low enough not to cause a phase change. Thus, the phase does not change unless the material is heated to a high temperature, so data is retained even when the power supply is switched off.
In order to effectively heat a phase change material by a write current, it is preferable to reduce a contact area between a lower electrode, which functions as a heater plug, and a recording layer, thereby reducing a heating region. To realize this, there is proposed a method in which an interlayer insulation film is arranged between the lower electrode of which top surface has a ring shape and a recording layer pattern in stripes, and the both are contacted via an aperture provided in the interlayer insulation film. See US 2004/0012009-A1; “Advances in Phase Change Memory Technology,” E. Varesi, A. Modelli, P. Besana, T. Marangon, F. Pellizzer, A. Pirovano, R. Bez, EPCOS (European Symposium Phase Change and Ovonic Science) 2004 Conf. Proceedings; and “Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology,” S. Hudgens, B. Johnson, MRS Bulletin, November 2004.
According to this method, the recording layer contacts only one portion of the ring-shaped lower electrode, and thus, the heating concentrates in one area. As a result, the heating of the phase change material by the write current is performed effectively, so that a phase change (reset) from a crystalline phase to an amorphous phase that particularly requires a large amount of current can be realized with a smaller amount of current.
FIG. 12 is a schematic plan view of a structure of relevant parts of a conventional non-volatile semiconductor memory device in which a contact area between the lower electrode and a recording layer is reduced. FIG. 13 is a schematic cross section taken along a line C-C shown in FIG. 12.
In the non-volatile semiconductor memory device shown in FIG. 12 and FIG. 13, a lower electrode 2, which functions as a heater plug, has a cylindrical shape. Thus, the plane shape of a top surface 2a has a ring shape. A bottom surface 2b of the lower electrode 2 is connected to a drain of a transistor (not shown) via a contact plug 4. The top surface 2a of the ring-shaped lower electrode 2 is covered with an interlayer insulation film 6.
The interlayer insulation film 6 is formed with an aperture 6a. In this portion, a region 3, which is one portion of the top surface 2a of the lower electrode 2, is exposed. The aperture 6a is commonly provided to two adjacent lower electrodes 2. The planar position of an edge 6b in a longitudinal direction is positioned in a region surrounded by the ring-shaped lower electrode 2.
A recording layer 8 composed of a phase change material is formed on the interlayer insulation film 6. Thus, the recording layer 8 contacts the top surface 2a of the lower electrode 2 via the aperture 6a, so that the contact area is limited to the area of the region 3 exposed by the aperture 6a. This limitation reduces the contact area. As a result, high heating efficiency can be obtained.
In the non-volatile semiconductor memory device shown in FIG. 12 and FIG. 13, however, one aperture 6a needs be formed for each two lower electrodes 2, which makes it difficult for the aperture 6a to be vertically positioned with the lower electrode. That is, when an independent aperture 6a having an island-like shape is to be formed, it becomes difficult to correctly control the position of the edge 6b. As a result, poor connection or the like easily occurs.
For example, as shown in FIG. 14, when the position of the aperture 6a is deviated from the original position to the right direction, the lower electrode 2 on the left side sometimes does not have any portion exposed by the aperture 6a. In this case, the lower electrode 2 on the left side and the recording layer 8 cannot contact, resulting in poor connection.
The problem of such poor connection can be solved to some extent by setting the length of the aperture 6a to be long. In this case, however, as shown in FIG. 15, when the position of the aperture 6a is deviated from the original position to the right direction, the lower electrode 2 on the right side becomes exposed in two regions by the aperture 6a. In such case, two current paths are formed between the same lower electrode 2 and the recording layer 8, so that a desired property cannot be obtained.